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fully accurate 12-/14-/16-bit v out dac spi interface 2.7 v to 5.5 v in a tssop preliminary technical data ad5025/45/65 rev. prb information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2007 analog devices, inc. all rights reserved. features low power dual 12-/14-/16 bit dac, 1lsb inl individual voltage reference pins rail-to-rail operation 2.7 v to 5.5 v power supply power-on reset to zero scale or midscale power down to 400 na @ 5 v, 200 na @ 3 v 3 power-down functions per channel power-down low glitch upon power up hardware power down lock out capability hardware ldac with ldac override function clr function to programmable code sdo daisy-chaining option 14 lead tssop applications process control data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators functional block diagrams interface logic sclk s ync din clr input register input register dac register dac register v dd gnd power-on reset dac a dac b buffer buffer v refa power-down logic v out a v out b ad5025/ad5045r/ad5065 ldac ldac 0 000-001 por sdo v refb pdl figure 1.ad5025/45/65 table 1. related devices part no. description ad5666 quad,16-bit buffered d/a,16 lsb inl, tssop ad5066 quad,16-bit unbuffered d/a,1 lsb inl, tssop ad5064/44/24 quad 16-bit nano dac, 1 lsb inl, tssop ad5063/62 16-bit nano dac, 1 lsb inl, msop ad5061 16-/14bit nano dac, 4 lsb inl, sot-23 ad5060/40 16-/14bit nano dac, 1 lsb inl, sot-23 general description the ad5025/45/65 are low power, dual 12-/14-/16-bit buffered voltage-out dacs offering relative accuracy specs of 1 lsb inl with individual reference pins and can operate from a single 2.7 v to 5.5 v supply. the ad5025/45/65 64 parts also offer a differential accuracy specification of 1 lsb. the parts use a versatile 3-wire, low power schmitt trigger serial interface that operates at clock rates up to 50 mhz and is compatible with standard spi?, qspi?, microwire?, and dsp interface standards. the reference for the ad5025/45 and ad5065 are supplied from an external pin. a reference buffer is also provided on-chip. the ad5025/45/64 incorporates a power-on reset circuit that ensures the dac output powers up zero scale or midscale and remains there until a valid write takes place to the device. the ad5025/45/65 contain a power-down feature that reduces the current consumption of the device to typically 330 na at 5 v and provides software selectable output loads while in power-down mode. the parts are put into power-down mode over the serial interface. total unadjusted error for the parts is <2 mv. both parts exhibit very low glitch on power-up. the outputs of all dacs can be updated simultaneously using the ldac function, with the added functionality of user-selectable dac channels to simultaneously update. there is also an asynchronous clr that clears all dacs to a software-selectable code0 v, midscale, or full scale. the part also features a power down lockout pin pdl , which can be used to prevent the dac from entering power down under any circumstances over the serial interface. product highlights 1. dual channel available in 14-lead tssop package with individual voltage reference pins. 2. 12-/14-/-16 bit accurate, 1 lsb inl. 3. low glitch on power-up. 4. high speed serial interface with clock speeds up to 50 mhz. 5. three power-down modes available to the user. 6. reset to known output voltage (zero scale or midscale). 7. power down lockout capability.
ad5025/45/65 preliminary technical data
table of conte n ts re vision hist or y rev. pr b | page 2 of 33
preliminary technical data ad5025/45/65
specifica t ions v dd = 2.7 v t o 5 . 5 v , r l = 2 k to gnd , c l = 20 0 pf t o gnd , 2. 2v v refin . v dd un less o t her w is e sp e c if ie d. al l sp e c if ic a t ion s t min to t max , u n l e ss ot h e r w i s e note d. table 2. p a r a me t e r m i n b gr ad e 1 t y p ma x unit c o nditions/c ommen t s st a t ic perfor m ance 2 r e solution 16 bits ad5065 14 ad5045 12 ad5025 r e la tiv e a c cu r a c y 0.5 1 lsb ad5065 t a = - 40c to +105c 0.5 1.5 ad5065 t a = - 40c to +125c 0.5 1 lsb ad5045 t a = - 40c to +105c 0.5 1.5 ad5045 t a = - 40c to +125c 0.5 1 lsb ad5025 t a = - 40c to +105c 0.5 1.5 ad5025 t a = - 40c to +125c diff er en tial nonline a r i t y 1 lsb ad5065/45/25: g u a r a n t e e d m o n o t o n i c b y d e s i g n t o tal unadjusted er r o r t u e 0.2 2 mv ad5065/45/25 t a = -40c to +105c 0.2 2 mv ad5065/45/25 t a = -40c to +125c o f f s e t e r r o r 1 9 m v all 0s loa d ed to d a c r e gist er o f f s et err o r drif t 2 v/c f u ll-s c ale er r o r ?0.2 ?1 % fsr a l l 1 s l o a d e d t o d a c r e g i s t e r g a in err o r 1 % fsr g a in t e mpera tur e c o efficie n t 2.5 ppm o f fsr/c dc p o w e r supply r e jec t ion ra t i o C80 db v dd 10% dc cr osstalk 0.5 lsb due to single - c hanne l full-sc ale output change , r l = 2 k to gn d or v dd 0.5 lsb/m a due to load cur r en t change 0.5 lsb due t o po w e ring do wn (per channel) o u tput cha r a c terist ics 3 o utput v o ltage r a nge 0 v dd v capaciti v e l o ad stabilit y 1 pf r l = 2 k, r l = 100 k and r l = dc o utput i m p e danc e 0.5 (normal mode) dc o utput i m p e danc e d a c in p o w e r do wn mode (output c o nnec t ed to 100k 100 k o utput impedanc e toleranc e 20 net w or k) (output c o nnec t ed t o 1k 1 k o utput impedanc e toleranc e 400 net w or k) s h o r t - c i r c u i t c u r r e n t 6 0 m a d a c = full scale , o/p shor ted to gnd 4 5 m a d a c = z e r o scale , o/p sho r te d to v dd po w e r - u p t i m e 4 . 5 s co m i n g o u t of pow e r - d ow n m o de v dd = 5 v dc psrr -92 db v dd 10%, d a c = full scale w i deband sfdr -67 db o u t p u t f r e q u e n c y = 1 0 k h z referenc e in p u t s r e f e r e nc e i n put r a nge 2.2 v dd v r e f e r e nc e c u r r e n t 30 50 a p e r d a c channe l v ref = v dd = 5.5 v r e f e r e nc e i n put i m pedanc e 120 k p e r d a c channe l lo g i c i n p u t s 3 i n put c u rr en t 4 3 a all d i gital inputs rev. pr b | page 3 of 33
1 2 3 4 5 6 ad5025/45/65 preliminary technical data
p a r a me t e r m i n b gr ad e 1 t y p ma x unit c o nditions/c ommen t s i n put l o w v o lta g e , v inl i n put h i gh v o lta g e , v in h p i n capacitanc e 2 0.8 4 v v pf v dd = 5 v v dd = 5 v l o gic outputs (sd o ) 3 o utput l o w v o lt age , v ol o utput h i gh v o l t age , v oh h i gh i m pedanc e l e ak age cu r r e n t h i gh i m pedanc e o utput capac i t a n c e v dd ? 1 0.4 0 . 2 5 2 v a pf i sin k = 2 ma i sou r ce = 2 ma power requir ement s v dd i dd (normal m o d e ) 5 v dd = 4.5 v to 5. 5 v i dd ( a ll p o w e r-d o wn m o d e s) 6 v dd = 4.5 v to 5. 5 v 2.7 5.5 3.2 4 0.4 1 v ma a all dig i tal inputs a t 0 or v dd d a c ac tiv e , ex cludes load cur r en t v ih = v dd and v il = gnd v ih = v dd and v il = gnd 1 temperature rang e is ?40c to +105c, typi cal at 25c.
linearity calculated u s ing a reduced c o de rang e of 512 to 65,024. output unloaded.
guarante e d by d e sign and characte riz a tio n ; no t pro d uctio n te s t ed .
to tal curre nt fl o w i n g into al l pins .
. interf ace inactive. a l l dac s active. dac o u tputs unloa d e d
. al l fo ur d a cs po we re d do wn
rev. pr b | page 4 of 33
preliminary technical data ad5025/45/65
ac charac teristics v dd = 2.7 v t o 5 . 5 v , r l = 2 k to gnd , c l = 20 0 pf t o gnd , v refin =4.096v unles s o t h e r w is e s p ecif ie d . al l sp e c if ica t ion s t mi n to t max , u n l e ss ot he r w i s e no te d. table 3. p a r a me t e r 1, 2 mi n ty p ma x unit c o nditions/c ommen t s 3 o utput v o ltage settling t ime 5 s ? to ? scale set t ling to 1 lsb , r l = 5k single ch annel upd a te including d a c c a libra t ion seque n c e o utput v o ltage settling t ime 14 s ? to ? scale set t ling to 1 lsb , r l = 5k all cha n nel upd a te inclu d ing d a c calibra t i o n sequenc e slew r a te 1.5 v/s digital-to -an a lo g glitch i m pulse 4 nv -s 1 lsb change around major car r y r e f e r e nc e f eedt h r o ugh ?90 db v ref = 2 v 0.1 v p - p , fr equenc y = 10 h z to 20 mh z sd o f eedthr o ugh 3 nv -s daisy- chai n mode; sd o load is 10 pf dig i tal f eedthr o ugh 0.1 nv -s digital cr os stal k 0.5 nv -s analog crossta l k 6 nv -s d a c-to -d a c cr osstalk 6.5 nv -s a c cr osstal k 6 nv -s a c psr r tbd multiplying bandwidth 340 kh z v ref = 2 v 0.2 v p - p t o tal har m onic distor tion ?80 db v ref = 2 v 0.1 v p - p , fr equenc y = 10 kh z o utput noise s p ec tr al d e nsit y 64 nv/h z d a c c o de = 0x8400, 1 kh z 60 nv/h z d a c c o de = 0x8400, 10 kh z o utput noise 6 v p - p 0.1 h z to 10 h z 1 guarante e d by d e sign and characte riz a tio n ; no t pro d uctio n te s t ed .
2 se e t h e t e rmin olo gy s e ct ion .
3 temperature range is ?40c to + 105c, typi cal at 25c.
rev. pr b | page 5 of 33
ad5025/45/65 preliminary technical data
timing characteristics a l l in p u t si gn als a r e s p eci f i e d w i th tr = tf = 1 n s / v (10% t o 90% o f v dd ) a n d t i m e d f r o m a vol t a g e le vel o f (v il + v ih )/2. s e e f i gur e 3 a n d fi g u r e 5 . v dd = 2.7 v t o 5.5 v . al l s p ec if ic a t ion s t min to t max , u n l e ss ot he r w i s e no te d. table 4. p a r a me t e r limit a t t min , t ma x v dd = 2.7 v t o 5. 5 v unit c o nditions/c ommen t s t 1 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 2, 3 t 17 3 t 18 3 t 19 3 t 20 20 10 10 16.5 5 5 0 1.9 10.5 16.5 0 20 20 10 10 10.6 22 5 8 0 20 ns min ns min ns min ns min ns min ns min ns min us min us min ns min ns min ns min ns min ns min ns min us min ns max ns min ns min ns min ns min sclk c y cle time sclk high time sclk lo w time sy nc t o sclk falling edge set - up time da ta set-up time da ta hold time sclk falling edge t o sy nc rising edge m i nimum sy nc high time (s ingl e channel upda t e ) m i nimum sy nc high time ( al l channel upda t e ) sy nc rising edge t o s c lk fall ig nor e sclk falling edge t o sy nc fall ig nor e ld a c pulse wid t h lo w sclk falling edge t o ld a c ri s i n g e d g e clr pulse wid t h lo w sclk falling edge t o ld a c falling edge clr pulse ac tiva tion time sclk rising edge t o sd o v a lid sclk falling edge t o sy nc ri s i n g e d g e sy nc rising edge t o s c lk rising edge sy nc rising edge t o ld a c falling edge pdl pulse wid t h ac tiva tio n time 1 ma xi m u m s c lk fre q uen c y i s 50 mh z a t v dd = 2.7 v to 5.5 v. guaranteed by de s i gn and characte riz a tio n ; no t pro d uctio n te s t e d .
2 mea s ure d with the loa d circuit o f figu re 16. t 16 d e termines the maximum sclk f r equency in d ais y-chain mod e .
3 dais y-chain mod e onl y.
2m a i ol 2m a i oh v oh (m i n ) to o u t p u t pi n c l 50 p f 0 52 98- 0 0 2 figure 2. lo ad ci rc uit for dig i ta l outp ut (sdo) timi ng sp eci f i cati ons rev. pr b | page 6 of 33
preliminary technical data ad5025/45/65
figure 3. ser i al wr it e ope r ati o n t 1 sc l k syn c di n sd o ld ac t 7 t 4 t 3 t 9 t 16 t 19 t 17 t 18 t 11 t 8 32 64 un de f i n e d i n p u t w o rd f o r da c n i n p u t w o r d f o r dac n i n p u t w o rd f o r dac n + 1 t 2 db0 db 3 1 db0 db31 db 3 1 db0 05 29 8- 00 4 fig u re 4. da is y - ch ain ti m i ng d i ag ra m rev. pr b | page 7 of 33
ad5025/45/65 preliminary technical data
absolute maximum ra tings
t a = 2 5 c , u n l e ss ot he r w i s e no t e d. table 5. p a r a me t e r r a ting v dd to gnd ?0.3 v to +7 v dig i tal i n put v o l t age to gnd ?0.3 v to v dd + 0.3 v v ou t to gnd ?0.3 v to v dd + 0.3 v v ref to gn d ?0.3 v to v dd + 0.3 v o p era t ing t e mp er a tur e r a nge i n dustr i al ?40c to +125c stor age t e mpera tur e r a nge ?65c to +150c j u nc tion t e mper a tur e ( t j max ) +150c tssop p a ck age p o w e r di ssip a ti on ( t j ma x ? t a )/ ja ja ther mal i m pedanc e 150.4c/w r e flo w s o lder ing p e ak t e mperatur e snp b 240c p b f r ee 260c esd caution
s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd (elec t r o sta t ic dischar g e) sensitiv e device . elec tr os t a tic char ges as high as 4000 v r e adily ac cumula te on the human bod y and t e st eq uipmen t and can dischar g e wi thout det e c t ion. although this pr oduc t f e a tur es pr o p r i etar y esd pr otec ti on ci r c uitr y , per m anen t dama ge may oc cur on dev i c e s subjec ted to high energy elec tr o s ta tic di scharge s . theref or e , p r oper esd pr ec autions a r e r e com m ended to av oid per f or man c e degrada t ion or l o ss of func tiona l it y . rev. pr b | page 8 of 33
preliminary technical data ad5025/45/65
pin conf igura t ion and fu nction descriptions 0000 - 0 0 6 1 2 3 4 5 6 7 a d 5 065/ 45/ 35 13 12 11 10 9 8 gn d v ou t b k to p v i e w ( n o t t o s cal e) pd l scl cl r vr e f b 14 di n ld a c sy n c v dd vr e f a v ou t a po r sd o figure 5. 14-lead t ssop (ru-14) ta ble 6. pi n f u nct i on d e s c ri pt i o ns p i n no . m n emonic description 1 ld a c p u ls ing th is p i n l o w a l lows a n y or al l d a c r e gi ste r s to be u p d a ted if the in put r e gi ster s hav e n e w d a t a . thi s a l l o ws a ll d a c out p uts to s i m u lta n e o u sly upd a te . a l ter n a t i v e l y , thi s pin can be tied permanen tly low . 2 a c ti ve l o w co n t rol i n put . thi s i s t h e f r ame sy nc h r on iz a t io n sign al f o r t h e i n put d a t a . wh en s y n c go es low , it p o w e r s o n t h e sclk a n d din b u ff er s and en a b les t h e i n put sh if t register . d a t a i s t r a n sf er red i n o n t h e f a ll in g e d ges of t h e n e x t 32 c l oc k s . i f sync is tak e n hi gh b e f o r e th e 32 nd f a llin g edg e , t h e r i sin g edge of sy nc ac ts as an in t e r r up t and t h e wr ite se que n ce i s igno r e d b y th e de vi ce . 3 sy nc p o w e r su p p ly i n put. th e s e p a r t s ca n be op e r a t ed fr om 2.7 v to 5 . 5 v , and the su p p ly s h o u l d b e d e c o up l e d with a 10 f capacitor i n par a llel with a 0.1 f capacitor to gnd . 4 v dd d a c a re fe re n c e i n p u t . t h i s i s t h e re fe re n c e v o l t a g e i n p u t p i n fo r d a c a . 5 v ref a analog o utput v o ltage fr om d a c a . t h e outp ut amplifier has rail-to - r a il opera t ion. 6 v ou t a por p o w e r- on r e set p i n. t y ing this pin to gnd po w e rs up the par t t o 0 v . t y ing this pin t o v dd po w e rs up the par t t o midscale . 7 sd o serial da ta o utput. c a n be used f o r da isy- chaini ng a number of these devic e s tog e t h er or f o r r e a d in g ba ck th e d a ta in t h e s h i f t r e g i s t er f o r di ag no s t i c p u rp oses . t h e s e ri al da ta is tr ans f e r r e d on t h e r i sing ed g e of sclk and is v a lid on the falling edge of the clock . 8 a s ynchr o nous clear i n put. t h e clr inp ut is falling e d ge sensitiv e . when clr is low , all ld a c pulses a r e ignor e d . whe n clr is ac tiv a t e d , the input r e g i st er and the d a c r e g i st er ar e upda t e d with the da ta c o n t a i n e d i n t h e c l r c o de r e g i s t er z er o , mid sc al e , o r fu ll sc a l e. d e f a u l t s e t t ing clears the output t o 0 v . 9 clr d a c b re fe re n c e i n p u t . t h i s i s t h e re fe re n c e v o l t a g e i n p u t p i n fo r d a c b. 10 v ref b analog o utput v o ltage fr om d a c b . t h e outp ut amplifier has rail-to - r a il opera t ion. 11 v ou t b gnd gr ound r e f e r e nc e p o in t f o r all cir c uitr y on the p a r t . 12 pdl the pdl pin is used to ensure h ard ware sh utdown lockout of the device under any circumstance. a logic 1 at the pl o pin will c a use the device to beha ve as norm al. t h e user may successfu l ly e nter software p o wer down over the serial interface while logic 1 is applie d to the pdl pin. if a logic 0 is applied to this pin, it will ensure th at the device cannot enter software power down under any circumstances. if th e device had pre vio u sly been place d in software p o wer d o wn mod e , a h i gh to low transi tion at the pdl pin will c a use the dac(s) to ex it p o wer down and the output th e l a st code in the dac register before the d evice entered software po wer d o wn. 13 din serial da ta i n put. t h is devic e has a 32-bi t shif t r e g i st er . da ta is clocked in t o the r e gister on the f a lling edge of the ser i al cl ock in put. 14 sclk s e r i al c l o c k i n pu t. d a ta i s c l oc ked i n to t h e i n put shif t r e g i st er on t h e f a lling edg e of the s e ri a l c l o c k i n p u t . da ta can be tr ansf err e d a t r a t e s of up t o 50 m h z . rev. pr b | page 9 of 33
ad5025/45/65 preliminary technical data
typical perf orm ance cha r acte ristics
tbd
figure 6. inl tbd
figure 7. dnl tbd
figure 8. tue rev. pr b | page 10 of 3 3
preliminary technical data ad5025/45/65
tbd
figure 9. inl v s . r e f e ren ce i n put vo lta g tbd
figure 1 0 . d n l v s . r e feren ce i n put vo ltage tbd
figure 11. tue vs. r e fere nce input volt age rev. pr b | page 11 of 3 3
ad5025/45/65 preliminary technical data
tbd
figure 1 2 . g a i n e r r o r and fu ll- sc ale e r ror vs. tem p er a t ure tbd
figure 1 3 . offs et e r ror v s . te mpe r atur e tbd
figure 1 4 . g a i n e r r o r and fu ll- sc ale e r ror v s . supply v o lt a g e rev. pr b | page 12 of 3 3
preliminary technical data ad5025/45/65
tbd
figure 1 5 . z e ro-s ca le e r ro r a n d offs et e rror v s . supply v o l t age tbd
figure 16. i dd his t o g ra m v dd = 3. 0 v tbd
figure 17. i dd his t o g ra m v dd = 5. 0 v rev. pr b | page 13 of 3 3
ad5025/45/65 preliminary technical data
fig u re 1 8 . he adr o o m at r a i l s v s . so urc e and si nk tbd
figure 1 9 . s o ur ce a n d sink cu rrent capability w i th v dd = 3 v
tbd
figure 2 0 . s o ur ce a n d sink cu rrent capability w i th v dd = 5 v
rev. pr b | page 14 of 33

preliminary technical data ad5025/45/65
tbd
figure 2 1 . supp ly c u rre nt v s . code tbd
figure 2 2 . supp ly c u rre nt v s . te mper a t ure tbd
figure 2 3 . supp ly c u rre nt v s . supply v o ltag e rev. pr b | page 15 of 3 3
ad5025/45/65 preliminary technical data
figure 2 4 . supp ly c u rre nt v s . logi c inp u t voltag e fig u re 2 5 . fu ll-s c a l e set t l ing t i m e tbd
figure 2 6 . po wer-o n r e s e t to 0 v
rev. pr b | page 16 of 33

preliminary technical data ad5025/45/65
tbd
figure 2 7 . po wer-o n r e s e t to m i ds c a le tbd
fi gure 28 . exi t ing po we r-down to mid s cale tbd
fig u re 2 9 . d i g i t a l-t o -a na log g lit ch i m puls e ( s e e f i g u re 3 4 ) rev. pr b | page 17 of 3 3
ad5025/45/65 preliminary technical data
tbd
fig u re 3 0 . a n al og cros s t alk tbd
figure 31. dac-to - d ac cr o sstal k tbd
figure 3 2 . 0.1 h z to 10 h z output n o is e p l ot rev. pr b | page 18 of 3 3
preliminary technical data ad5025/45/65
tbd
figure 33. typ i c a l s u pply cur r ent vs. fr equen c y @ 5.5 v 1 tbd
fi gure 34 . di gi t a l - t o -anal o g g l i t ch en ergy tbd
figure 3 5 . n o ise sp ectr a l density, i n ter n al r e fer e nc e rev. pr b | page 19 of 3 3
ad5025/45/65 preliminary technical data
tbd
fig u re 3 6 . t o t a l ha rm oni c d i s t ort i on tbd
figure 37. s e ttling time vs. cap a c i tive load tbd
figure 3 8 . ha rdw a r e clr tbd
figure 39. mu ltip lying band width rev. pr b | page 20 of 3 3
preliminary technical data ad5025/45/65
tbd
fi gur e 40 .typic al output sl e w r a te rev. pr b | page 21 of 3 3
ad5025/45/65 preliminary technical data
theor y of opera tion d/a secti o n outpu t am plifier the ad5025 /4 5/65 a r e sin g le 12-/14 an d 16 -b i t , s e r i al in p u t, t h e o u t p u t b u f f er a m p l if ier can g e n e ra t e ra il-t o-ra il v o l t a g es o n v o l t a g e o u t p u t d a cs. the p a r t s o p era t e f r o m su p p l y v o l t a g es o f i t s o u t p u t , which g i v e s a n ou t p u t ra n g e o f 0 v to v dd . th e 2.7 v t o 5.5 v . da t a is wr i t t e n to th e ad5025/4 5 /65 in a 32-b i t a m plif ier is c a p a b l e o f dr iving a lo ad o f 2 k in p a ra l l e l w i t h w o r d f o r m a t via a 3-wir e s e r i al in t e r f ac e . th e ad5025/45 an d 1,000 pf t o gnd . th e s o ur ce and sin k c a p a b i l i ties o f th e ou t p u t ad5065 i n c o rpo r a t e a po w e r - o n r e se t c i r c u i t t h a t e n s u r e s th e a m plif ier can b e s e en i n (tb d ) an d (tb d ) . th e s l ew ra t e i s 1. 5 d a c output p o we r s up to a k n ow n out - put s t a t e ( m i d s c a l e or v/s wi th a ? to ? s c al e s e t t l i ng tim e o f 10 s. zer o - s ca le, s e e t h e o r d e r i ng g u i d e ) . the de v i ce s al s o ha ve a s o f t wa re p o w e r - do w n mo de t h a t r e d u c e s t h e ty p i ca l c u r r e n t co nsu m p t ion to less t h an 1 a . serial interface b e c a u s e th e i n p u t c o d i n g t o th e d a c i s s t r a i g h t b i n a r y , th e i d e a l the ad5025 /45 / 65 has a 3-wir e s e r i al in t e r f ace ( sy n c , sclk, o u t p u t v o l t a g e when usin g an ext e r n al r e f e r e n c e is g i v e n b y a nd d i n) tha t is co m p a t i b le wi th s p i, qs p i , and mi cro w i r e ? d ? in ter f ace st a n d a r d s as w e l l as most ds p s . s e e f i gur e 3 fo r a v out = v refin ? n ? t i mi n g di a g ra m o f a typ i c a l wr i te s e q u e n ce. ? 2 ? standalone mode the ide a l o u t p ut v o l t a g e w h en usin g a nd i n t e r n al r e fer e n c e is gi v e n b y the wr i t e s e q u e n ce b e g i n s b y b r in g i n g t h e sy n c lin e lo w . d a t a f r o m t h e d i n li n e is clo c k e d i n to t h e 32- b i t s h if t r e g i s t er o n t h e v out = 2 v refout ? ? d ? ? fal l in g e d g e o f s c lk. the s e r i al c l o c k f r eq uen c y ca n be as hig h ? 2 n ? as 50 mh z, ma kin g t h e ad502 5/45/65 co m p a t i b le wi th hig h s p eed d s p s . o n th e 32 nd fal l in g c l o c k e d g e , t h e l a s t da t a b i t is w h er e:
d = decimal eq ui valen t o f t h e b i na r y co de tha t is lo aded t o t h e c l oc k e d in a n d t h e p r ogra mm ed fun c ti o n i s e x ecu t ed , th a t i s , a
c h a n g e in d a c r e g i s t er co n t en ts a nd/o r a c h ang e in t h e mo de d a c r e g i s ter . 0 t o 65,535 f o r a d 5065 (16 b i t s). n = t h e d a c re s o lut i on . o f o p era t io n. a t this s t a g e , t h e sy n c line can b e k e pt lo w o r b e b r o u g h t hig h . i n ei t h er cas e , i t m u s t b e b r o u g h t hig h fo r a dac architecture m i n i m u m of 1 5 ns b e f ore t h e n e x t w r ite s e qu e n c e s o t h a t a the d a c a r c h i t ec t u r e o f t h e ad5065 co n s is ts o f tw o ma t c h e d fal l in g e d g e o f sy n c ca n i n i t i a t e t h e n e xt wr i t e s e q u en c e . d a c s e c t io n s . a sim p l i f i e d circ ui t di a g ra m is s h o w n i n f i gur e b e ca us e t h e sy n c b u f f er dra w s m o r e c u r r en t w h e n v in = 2 v 41. the f o ur ms bs o f th e 16 -b i t da t a w o r d a r e deco de d t o dr ive t h a n i t do es w h en v in = 0.8 v , sy n c s h o u l d be idle d lo w 15 swi t ch es, e1 t o e15. e a ch o f t h es e s w i t ch es c o nn e c ts o n e o f b e tw e e n wr i te s e q u ences fo r e v en lo w e r p o w e r o p era t ion o f t h e 1 5 m a tc he d re s i stor s to e i t h e r g n d or v ref bu f f e r output . th e p a r t . a s is m e n t io n e d p r e v io usly , h o we v e r , sy n c mu s t b e re m a i n i n g 1 2 bit s of t h e d a t a w ord d r ive s w itc h e s s 0 to s 1 1 of a b r o u g h t hig h a g a i n j u s t b e fo r e t h e n e xt wr i t e s e q u en c e . 12-b i t v o l t a g e m o de r - 2r ladder n e tw o r k. v out 2r 2r 2r 2r 2r 2r 2r ta ble 7. co mm a nd defi ni t i on s 047762- 027 12-bit r-2r ladder four msbs decoded into 15 equal segments figure 4 2 . d a c lad d er stru cture reference buffer the ad5025 /45 a nd ad5065 op era t e wi t h a n ext e r n al r e fer e n c e. e a ch o f t h e tw o on b o a r d d a c s wi l l h a ve a de di ca te d v o l t a g e r e fer e n c e p i n. i n e i t h er cas e t h e r e fer e nce in p u t p i n has a n i n p u t ra n g e o f 2 v t o v dd . this in pu t v o l t a g e is t h en us e d t o p r o v ide a b u f f er e d r e fer e n c e fo r t h e d a c co r e . s0 v ref s1 s11 e1 e2 e15 c o mmand description c3 c2 c1 c0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 w r ite to i n put reg i ster n upda te d a c r e g i ster n w r it e t o i n put reg i st er n, upda t e all (s of t w ar e ld a c ) w r ite to and upda te d a c channel n p o w e r do wn/pow er up d a c l o ad clear c o de r e g i ster lo a d l d ac re g i s t e r r e set (po w er - o n r e set) s e t up dcen r e g i ster (daisy chain enable) s e t up dio dir e c t ion and v a lue r e ser v ed rev. pr b ? page 22 of 3 3
preliminary technical data ad5025/45/65
tab l e 8. add r ess command s a ddr ess (n) s e lec t e d d a c channel a3 a2 a1 a0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 d a c a d a c b r e ser v ed r e ser v ed all d a cs rev. pr b | page 23 of 3 3
ad5025/45/65 preliminary technical data
inpu t shift register the ad5025 /45 / 65 in p u t shif t reg i s t er is 32 b i ts wide (s ee f i gur e 43). th e f i rs t fo ur b i t s a r e do n t ca r e s. th e n e xt fo ur b i t s a r e t h e command b i ts, c3 t o c0 (s e e t a b l e 8), fol l o w e d b y t h e 4- b i t d a c addr ess b i t s , a3 t o a0 (s e e t a b l e 9) and f i nal l y t h e b i t da ta-w o r d . th e da ta-w o r d com p r i s e s ei t h er 12-/14 o r 16-b i t in p u t co de fol l o w e d b y 8-/6 o r 4 do n t c a r e b i ts fo r t h e ad5025/45 /65 (s ee f i gur e 43). th es e da ta b i ts a r e tra n sf er r e d t o th e d a c r e gis t er o n th e 32 nd fal l in g e d ge o f scl k . db31 ( m s b) sync interrupt i n a n o rm al w r i t e seq u en ce , t h e sy n c line is k e p t l o w f o r a t le as t 32 fal l i n g e d g e s o f sclk, and t h e d a c is up da t e d o n t h e 32 nd fal l in g e d g e . h o w e v e r , if sy n c i s brou g h t h i g h b e f ore t h e 32 nd fal l in g e d g e , t h is ac ts as an i n t e r r u p t t o t h e wr i te s e q u ence . the s h if t r e g i s t e r is r e s et, an d t h e wr i t e s e q u e n c e is s e en as in vali d . n e i t her a n u p da t e o f t h e d a c r e g i s ter co n t e n ts n o r a c h a n g e in t h e o p era t in g m o de o c c u r s (s ee f i gu r e 46). db 0 ( l s b ) c3 c2 c1 c0 a3 a2 a1 a0 d15 d 1 4 d13 d 12 d11 d 1 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x da t a b i t s 0529 8- 02 5 0529 8- 025 05 29 8- 0 2 5 c 3 c 2 c 1 c 0 a 3 a 2 a 1 a 0 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x x x x x x x x x x c 3 c 2 c 1 c 0 a 3 a 2 a 1 a 0 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x x x x x x x x x x x x co m m and bi t s ad dre s s bi t s fi gur e 43 . ad5 065 input re gi ste r co nt e n t db 31 ( m s b) db 0 ( l s b ) da t a b i t s co m m and b i t s add re s s b i t s fi gur e 44 . ad5 045 input re gi ste r co nt e n t db 31 ( m s b) db 0 ( l s b ) da t a b i t s co m m and b i t s add re s s b i t s fi gur e 45 . ad5 025 input re gi ste r co nt e n t sc l k db 3 1 db 0 db 3 1 db 0 sy n c di n i n v a l i d w ri t e s e q ue nce : v a l i d w ri t e s e q ue nce , o u t p ut up dat e s syn c h i g h b e f o r e 3 2 n d f a l l i n g ed g e o n t h e 3 2nd f al l i ng e d g e figure 46. sync interrup t fa ci li ty rev. pr b | page 24 of 3 3 0529 8- 026
preliminary technical data ad5025/45/65
dais y-cha i ning f o r sys t em s t h a t co n t ain s e v e ra l d a cs, o r w h ere t h e us er wish es t o r e ad b a ck t h e d a c con t e n ts fo r di a g nos t ic p u r p os es, t h e s d o p i n c a n b e us e d to da i s y - cha i n s e ver a l de vices to get h e r a nd p r o v ide s e r i a l r e ad- b ack. the da isy - cha i n m o de is enab le d t h r o ug h a s o f t wa r e exe c u t a b le d c en (da i sy c h a i n ena b le) comman d . c o mma nd 1000 is r e se r v ed f o r th i s d c en fun c ti o n (see t a b l e 7). t h e d a i s y- c h a i n m o de is enab le d b y s e t t in g a b i t (d b1) in t h e d c en r e g i st er . the def a u l t s e t t i n g is s t andalon e m o de , w h er e b i t d c en = 0 . t a b l e 9 sh o w s ho w t h e st a te o f t h e b i t s co r r es p o n d s t o t h e m o de of op e r a t i o n of t h e d e v i c e . the s cl k is con t i n uo us ly a p pli e d t o t h e i n p u t shif t r e g i s t er wh e n sy n c is lo w . i f m o r e than 32 c l o c k p u ls es a r e a p p l ied , t h e da t a r i p p les o u t o f t h e shif t r e g i st er a nd a p p e a r s o n t h e s d o line. t h is da t a i s clo c k e d o u t on t h e r i sin g e d ge o f sclk and is v a lid o n t h e falli n g ed g e . b y co n n ect i n g th i s lin e t o th e d i n in p u t o n t h e ne xt d a c i n t h e cha i n, a m u l t i- d a c in t e r f ace is co n s t r uc t e d . e a ch d a c in t h e s y s t em r e q u ir es 32 clo c k p u ls es; t h er efo r e , t h e t o t a l n u m b er o f clo c k c y cles m u s t e q ual 32 n, w h er e n is t h e to t a l n u m b er o f de vices in t h e cha i n. w h en t h e s e r i al t r a n sfer t o al l de v i ces is co m p le t e , sy n c is tak e n h i g h . th i s p r ev e n t s a n y f u r t h e r da t a f r o m b e i n g c l ock e d in t o t h e in p u t shif t r e g i s t er . if sy n c is t a k e n hig h b e fo r e 32 clo c ks a r e clo c k e d i n to t h e p a r t , i t is co n s i d er e d a n i n v a li d f r a m e a nd t h e d a t a is dis c a r d e d . the s e r i al c l o c k ca n be co n t in u o us o r a ga t e d c l o c k. a co n t in uo us scl k s o ur ce can be us ed o n l y if t h e sy n c ca n be h e ld lo w f o r th e co rr ect n u m b e r o f c l oc k c y c l e s . i n g a t e d c l ock m o de , a b u rst clo c k co n t a i nin g t h e exac t n u m b er o f clo c k c y cle s m u st b e us e d , and sy n c m u st b e t a ken hi g h a f ter t h e f i na l cl o c k to l a tc h t h e d a t a . power down lockout the ad5025 /45 / 65 contains a 1 - bit digital inpu t pin pdl . w h en ac t i v a t e d, t h e p o w e r do w n lo ck o u t p i n ( pdl ) d i sa b l es s o f t ware sh ut dow n u n de r an y c i rc u m st anc e s t h e u s e r shou l d h a rdw i re t h e pdl p i n t o a log i c lo w ( th us p r ev en t i ng s u bs e q uen t s o f t wa r e p o w e r do wn) o r log i c hig h (the p a r t ca n be place d in p o w e r do wn m o de o v e r t h e s e r i al i n t e r f ace). sh o u l d th e use r d e ci de t o tra n s i ti o n th e pdl p i n f r o m l o gi c h i gh t o a lo g i c lo w d u r i ng a va li d wr i te s e q u ence, t h e de vice w i l l r e sp ond imm e di a t e l y a nd t h e c u r r en t w r i t e s e q u e n ce wi l l b e ab o r t e d . p o in ts t o n o t e ab o u t t h e pdl f e at u r e i s t h at 1. if a pdl i s ge ne r a te d ( i. e. a hi g h to l o w t r ans i t i on) w h i l e a val i d wr i t e s e q u e n ce is on g o in g t h e n t h e wr i te wi l l b e ab o r t e d . the us er w i l l n e e d t o r e wr i t e t h e c u r r en t wr i t e comman d a g a i n. 2. if a pdl is g e n e ra t e d , w h i l s t t h e d a c(s) a r e in p o w e r do w n mo de , t h e n t h e d a c (s) wi l l come o u t o f p o w e r do w n ( i . e . al l p o w e r do w n r e g i s t ers g et r e s et t o 0000 ) t o th e last valid s t o r e d d a c val u e . a s lon g, as pdl re m a i n s a c t i v e s o f t w a re p o we r d o w n i s d i s a bl e d . 3. af t e r t h e pdl is taken f r o m a lo w to a hig h s t a t e , t h en a l l d a c cha n nels wi l l r e ma i n i n n o r m a l m o de and t h e us er wi l l ha v e t o r e -is s u e a s o f t wa r e p o w e r do wn c o m m a nd to t h e c o n t ro l re g i ste r i n ord e r to p o we r do wn t h e r e q u ire d cha n nels.. 4. t r a n s i ti o n i n g th e pdl f r o m a lo w to a hig h wil l dis a b l e t h e fe a t u r e imm e di a t e l y . 5. if plo a nd clr a r e g e n e r a t e d a t th e sa m e ti m e , th e n clr sig n al w i l l ca u s e t h e dac r e g i ster t o cha n g e as p e r t h e c l e a r c o n t e n t reg i s ter a nd t h en d a cs wi l l c o me out of p o we r d o w n . 6. if plo , clr a nd ld a c a r e gener a te d a t s a m e t i me th en clr w i ll h a v e h i g h e r p r eced en ce o v e r ld a c a nd plo this cas e wil l be s a me as cas e 2 m e n t io ned ab o v e. 7. the us er is r e co mmende d t o har d w i r e t h e p i n to a log i c hig h o r lo w t h er eb y ei t h er ena b li n g o r dis a b l in g th e f e a t ur e . power-on reset the ad5025 /45 / 65 co n t ain s a p o w e r - o n r e s et cir c ui t tha t co n t r o ls t h e o u t p u t v o l t a g e d u r i n g p o w e r - u p . by co nn e c t i n g t h e po r p i n lo w , the ad5025/45 /6 5 o u t p u t p o w e rs u p t o 0 v ; b y co nn ec t i n g the po r p i n hig h , t h e ad5025/45 /65 o u t p u t p o w e rs u p t o mid-s c ale . the o u t p u t r e ma in s p o w e r e d u p a t this l e v e l un t i l a vali d wr i t e s e q u e n c e is made t o t h e d a c. this is us ef u l in a p plic a t io n s w h er e i t is im p o r t a n t t o k n o w t h e st a t e o f t h e o u t p ut o f t h e d a c w h i l e i t is in t h e p r o c e s s o f p o w e r i n g u p . ther e is als o a s o f t wa r e exe c u t ab le r e s et f u n c t i on t h a t r e s ets t h e d a c t o t h e p o w e r - o n r e s e t co de . c o mman d 0 111 is r e s e r v ed f o r th i s r e se t fun c ti o n (see t a b l e 7). a n y ev en t s o n ld a c or clr d u r i ng p o we r - on re s e t are i g n ore d. power-down modes the ad5025 /45 / 65 co n t ain s f o u r s e p a ra t e m o des o f o p era t io n. c o mmand 0100 is r e s e r v ed f o r th e p o w e r - do wn f u n c tion (s ee t a b l e 7). th es e m o des a r e s o f t wa r e -p r o g r a mma b l e b y s e t t i n g t w o b i t s, b i t d b 9 and bi t d b 8 , i n t h e c o n t r o l r e g i st er (r efer t o t a b l e 12) . t a b l e 11 sh o w s h o w t h e st a t e o f t h e b i ts co r r es p o n d s t o th e m o d e o f o p e r a t i o n o f th e d e v i ce . a n y o r all d a c s (d a c a a nd d a c b) ca n b e p o w e r e d do wn to t h e s e l e c t e d m o de b y s e t t in g t h e co r r es p o ndin g f o ur b i t s (d b3, d b 2, d b 1, d b 0) t o 1. s e e t a b l e 12 fo r t h e con t e n ts o f t h e in p u t shif t reg i s t er d u r i n g p o we r - d o w n / p owe r - u p op e r at i o n . rev. pr b | page 25 of 3 3
ad5025/45/65 preliminary technical data
w h en b o t h b i t d b 9 a n d b i t d b 8 , i n th e c o n t r o l r e g i s t e r a r e s et to 0 , t h e p a r t wor k s nor m a l ly w i t h i t s nor m a l p o w e r c o nsu m pt i o n of tbd a t 5 v . h o w e v e r , f o r th e th r e e po w e r - do wn m o d e s , t h e s u p p ly c u r r en t f a l l s t o tbd a t 5 v ( tbd a t 3 v). n o t o n ly do es t h e s u p p ly c u r r en t fal l , b u t t h e ou t p ut s t a g e is al s o in ter nal l y s w itc h e d f rom t h e output of t h e am pl i f i e r to a r e s i stor ne t w or k o f kn o w n val u e s . this has t h e ad va n t a g e t h a t t h e o u t p ut im p e dan c e o f t h e p a r t is k n o w n w h i l e t h e p a r t is in p o w e r - do wn m o de . ther e a r e t h r e e dif f er en t o p t i o n s. the o u t p u t is co nn ec t e d in t e r n al l y t o gnd t h r o u g h ei ther a 1 k o r a 100 k re s i stor , or it i s l e f t op e n - c i r c u it e d ( t h r e e - s t a te ) . t h e output st age is i l l u st r a t e d i n f i g u re 4 7 . t h e bi a s ge ne r a tor , output am pl i f i e r , re s i stor st r i ng , a n d ot he r a s s o cia t e d lin e a r ci r c ui tr y a r e s h u t do wn w h en t h e p o w e r - d o wn mo d e i s a c t i v a t e d. h o w e v e r , t h e con t e n t s o f t h e d a c reg i st er a r e u n a f f e ct ed wh e n i n po w e r - d o w n . th e t i m e t o e x i t p o w e r - do w n is typ i c a l l y 2.5 s f o r v dd = 5 v a nd v dd = 3 v (s ee f i gur e 28). an y com b ina t ion o f d a cs ca n b e p o w e r e d u p b y s e t t i n g pd1 a nd p d 0 t o 0 (no r mal o p er a t ion). th e o u t p ut p o w e rs u p t o t h e val u e i n t h e in pu t r e g i s t er ( ld a c l o w) o r t o t h e v a lue in t h e d a c r e g i s ter b e fo r e p o w e r i n g do w n ( ld a c hig h ). rev. pr b | page 26 of 3 3
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table 9. dcen (daisy -chain en able) register (db1) (db0) ac t i o n 0 0 standal o ne mode (defaul t ) 1 0 dcen mode table 10. 3 2 -bit input shift r e gister content s for da i s y-ch a i n ena b l e a n d refere nce set - up f u nct i on msb lsb db31 t o db28 db 27 db 26 db 25 db 24 db 23 db 22 db 21 db 20 db 2 to db 19 db 1 db 0 x 1 0 0 0 x x x x x 1/0 1/0 don t car e s command bits (c3 to c0) addres s bits (a3 to a0) don t car e s dcen re g i s t e r table 11. mo de s of o p eration db 9 db 8 o p er a t ing mo d e 0 0 nor m al opera ti on p o w e r - do w n modes 0 1 1 k to gnd 1 0 100 k to gnd 1 1 thr e e - st a t e ta ble 12. 3 2 -bi t input shi f t r e gi s t er cont ent s for power- up /power-dow n f u nct i on m s b l s b db31 t o db28 db27 db26 db25 db 24 db23 db22 db21 db20 db10 t o db19 db9 db8 db 4 to db 7 db 3 db 2 db 1 db 0 x 0 1 0 0 x x x x x pd1 pd0 x x x dac b dac a dont com m a n d bi ts (c2 t o c0) addres s bi ts ( a 3 to a 0 ) dont power-down dont power-down/ p ower- u p channel s e lection care s dont cares care s mo de care s s e t bi t to 1 to s e l e c t figure 47. output s t age du ring powe r - down rev. pr b | page 27 of 3 3
ad5025/45/65 preliminary technical data
clear code register the ad5025 /45 / 65 has a ha r d wa r e clr p i n tha t is an as y n chronou s cl e a r in p u t. t h e clr in p u t is f a l l in g e d ge s e ns i t ive. br i n g i ng t h e clr li n e lo w c l ea r s th e co n t en t s o f t h e in p u t r e g i s t er and t h e d a c r e g i s t ers t o t h e da t a co n t ai n e d in t h e us er -co n f i gura ble clr r e g i s t er an d s ets t h e a n alog ou t p uts a c c ord i n g l y . ( s e e ta b l e 1 3 ) th i s fun c ti o n ca n b e used in s y s t em c a l i b r a t i o n to l o ad ze ro s c a l e, m i ds c a l e , or f u l l s c a l e to a l l cha nne ls t o g e t h er . th e s e cle a r c o de va l u es a r e us er - p r og ra mma b l e b y s e t t i n g tw o b i ts, b i t d b 1 an d b i t d b 0, i n t h e c o n t ro l re g i ste r ( s e e ta b l e 1 3 ). the def a u l t s e t t i n g cle a rs t h e o u t p u t s t o 0 v . c o mmand 0101 is r e s e r v ed f o r l o adin g t h e c l ea r co de r e g i st er (s e e t a b l e 7). the p a r t exi t s cl e a r co de m o d e o n t h e 32 nd fal l in g edg e o f t h e n e xt wr i t e t o t h e p a r t . i f clr is ac t i va te d d u r i n g a wr i te seq u en ce , th e wri t e i s a b o r t e d . th e cl r p u ls e a c ti v a ti o n t i m e t h e f a ll i n g ed g e o f cl r to w h e n t h e ou t p u t st a r t s to c h ange i s t y p i c a l l y tbd ns. h o we ve r , i f o u t s i d e th e d a c lin e a r r e g i o n , i t t y p i call y tak e s tb d ns a f ter exe c u t ing cl r f o r th e o u t p u t t o s t a r t c h a n g i n g (s e e f i gur e 38). s e e t a b l e 14 fo r co n t e n ts o f t h e in p u t s h if t r e g i st er d u r i n g t h e l o a d i n g cl e a r c o d e re g i ste r op e r a t i o n ldac funct i o n the o u t p u t s o f a l l d a cs ca n b e u p da te d si m u l t a n e o usly usin g t h e h a rdw a re ld a c pi n . s y nch ronou s ld a c : a f t e r n e w d a ta is r e a d , t h e d a c r e gi s t e r s a r e u p da te d on t h e fal l i n g e d g e o f t h e 32 nd scl k p u ls e . ld a c ca n be pe rm a n en tl y lo w o r p u lsed a s in f i g u r e 3 as y n c h r o n o u s ld a c : th e o u t p u t s a r e n o t u p da t e d a t t h e s a me t i m e t h a t t h e in p u t r e g i s t ers a r e wr i t t e n t o . w h en ld a c go e s lo w , t h e d a c r e g i s t ers a r e u p da t e d wi t h t h e co n t en ts o f t h e in p u t r e g i s t er . al ter na t i ve ly , t h e o u t p uts o f al l d a cs can b e up da t e d sim u l t an eo us l y usin g the s o f t wa r e ld a c f u n c tio n b y wr i t in g t o i n p u t r e g i s ter n a nd u p da t i ng a l l d a c r e g i s t ers . c o mmand 0010 is r e s e r v e d f o r this s o f t wa r e ld a c fun c ti o n . an ld a c r e g i s t er g i ves t h e us er ext r a f l exi b i l i t y an d c o n t r o l o v er t h e ha r d war e ld a c p i n. this r e g i s t er al lo ws t h e us er t o s e le c t w h ich com b i n a t io n o f ch a nne ls t o si m u l t a n e o us ly u p d a te w h en t h e ha r d w a r e ld a c p i n i s e x ecu t ed . s e t t i n g t h e ld a c bit r e g i s t er t o 0 fo r a d a c cha nn e l m e an s t h a t t h is cha nne l s up da te i s co n t r o lled b y th e ld a c p i n. i f this b i t is s et t o 1, this c h a nne l up d a te s s y nch ronou sly ; t h at i s , t h e d a c re g i s t e r i s up d a te d af te r n e w d a t a i s re a d , re g a rd l e s s of t h e s t a t e of t h e ld a c pi n . i t ef fe c t i v e l y s e es t h e ld a c p i n as bein g tied lo w . (s e e t a b l e 15 fo r t h e ld a c r e g i s t er m o de o f o p era t i o n.) this f l exi b i li ty is us ef u l in a p pl ic a t io n s w h er e t h e us er wa n t s t o sim u l t an e o us ly u p da te s e le c t cha nne ls w h i l e t h e r e s t o f t h e channe ls a r e sy n c hr on o u sly u p da t i ng. w r i t in g t o the d a c usin g co mma nd 0110 lo ads th e 4 - b i t ld a c r e g i s t er (d b3 t o d b 0). the def a u l t f o r eac h c h a nne l is 0; tha t is, th e ld a c p i n w o rks no r m al ly . s e t t in g t h e b i ts t o 1 m e a n s t h e d a c ch an n e l i s up d a te d re g a rd l e ss of t h e st ate of t h e ld a c p i n. s e e t a b l e 1 6 fo r t h e co n t e n ts o f t h e in p u t shif t r e g i s t er du r i n g t h e l o a d ld a c r e g i s t er mo de o f o p era t io n. power supply bypass ing and gr ounding w h en acc u rac y is im p o r t an t i n a cir c ui t, i t is hel p f u l to ca r e f u l l y c o ns i d e r t h e p o we r supply an d g rou nd re tu r n l a y o ut on t h e bo a r d . the p r in t e d cir c u i t bo a r d co n t ainin g t h e ad5666 sh o u l d ha v e s e p a ra t e analog a nd dig i ta l s e c t io n s . i f t h e ad5666 is in a sys t em w h er e ot h e r de v i ces r e quir e a n a g nd - t o-d g nd c o n n e c t i on , t h e c o n n e c t i on s h o u l d b e m a d e a t one p o i n t on ly . this g r o u nd p o in t sh o u ld b e as clos e as p o s s i b l e t o t h e ad5025/45 /65. t h e p o w e r s u p p l y t o th e ad502 5/45/65 s h o u l d be b y pa s s e d w i th 1 0 f an d 0.1 f ca p a ci t o rs. the ca p a c i t o rs sh ou ld p h ysical l y b e a s c l o s e a s po s s i b l e t o th e d e v i ce , w i th th e 0 . 1 f c a pa c i t o r ide a l l y r i g h t u p a g a i ns t t h e de vi ce . th e 10 f c a p a ci t o rs a r e t h e ta n t al um be a d type . i t i s im po r t a n t tha t t h e 0. 1 f ca pa ci t o r h a s lo w ef fe c t i v e s e r i es r e sis t a n c e (es r ) a nd lo w ef fe c t i v e s e r i es ind u c t an c e (es i ), s u c h as is typ i cal o f co mm o n cera mic typ e s of ca p a ci t o rs. this 0.1 f ca p a ci t o r p r o v ides a lo w im p e dan c e p a t h t o gr o u n d f o r h i gh f r eq ue n c i e s ca used b y tra n s i en t curr e n t s d u e t o in ter nal log i c swi t c h in g. the p o wer su p p ly lin e sh o u ld h a v e as la rge a t r ace as p o ssib le to p r o v ide a lo w i m p e dan c e p a t h a nd r e d u ce g l i t ch ef fe c t s o n t h e s u p p l y lin e . c l o c ks an d o t h e r fas t swi t chin g dig i t a l sig n als shou l d b e sh i e l d e d f rom ot he r p a r t s of t h e b o a r d b y d i g i t a l g rou nd. a v oi d c r o s s o ve r of d i g i t a l an d an a l o g s i g n a l s i f p o ss ibl e . w h en t r aces cr os s o n o p p o si t e sides o f t h e bo ar d , en s u r e t h a t th ey r u n a t ri g h t a n gle s t o ea ch o t h e r t o r e d u ce f eed th r o u gh ef fe c t s t h r o u g h t h e b o a r d . th e b e s t b o a r d la you t t e chniq u e is t h e micr os t r i p te chniq u e, w h ere t h e co m p o n en t side o f t h e b o a r d is de di ca te d to t h e g r o u nd plan e o n ly and t h e sig n a l t r aces a r e place d o n t h e s o lder side . h o w e v e r , t h is is n o t alw a ys p o s s i b le wi t h a 2-l a yer bo a r d . rev. pr b | page 28 of 3 3
preliminary technical data ad5025/45/65
t a bl e 13. c l e a r c o de r e g i st e r clear c o de reg ist er clears t o c o de db 1 db 0 cr1 cr0 0 0 1 1 0 1 0 1 0x0000 0x8000 0xffff no opera tion table 14. 3 2 -bit input shift r e gister content s for clear co de function msb lsb db31 t o db28 db 27 db 26 db 25 db 24 db 23 db 22 db 21 db 20 db 2 to db 19 db 1 db 0 x 0 1 0 1 x x x x x 1/0 1/0 don t car e s c o mmand bits ( c 3 t o c0) a ddr es s bits ( a 3 t o a0) don t car e s clear c o de r e gister ( c r1 to cr0 ) table 15. ldac o v er write definitio n load d a c regi st er ld a c op e r a t i o n ld a c bits (d b3 t o db0) ld a c pi n 0 1 1/0 x don t car e d e ter mined b y ld a c pin d a c channels u p d a te , ov er r i d e s the ld a c pin. d a c c h anne ls see ld a c as 0. table 16. 3 2 -bit input shift r e gister content s for ldac overwrit e function msb lsb db31 db 4 to to db 28 db 27 db 26 db 25 db 24 db 23 db 22 db 21 db 20 db 19 db 3 db 2 db 1 db 0 x 0 1 1 0 x x x x x x x d a c b d a c a dont command bits (c 3 to c0) add r ess bits (a3 t o a0) dont setting ldac bit to 1 ov erride ldac pin car e s dont cares car e s rev. pr b | page 29 of 3 3
ad5025/45/65 preliminary technical data
s e r i al wr i t e o p e r a t io n is p e r f o r m e d t o t h e d a c. pc7 is t a k e n h i gh a t t h e en d o f th i s p r oced ur e . ad5024/44/6 4 to 80c51/80 l51 interface f i gur e 50 sh o w s a s e r i al in t e r f ac e betw e e n t h e ad5024/44/64 a nd t h e 80c51 /80l51 micr o c on tr ol ler . th e s e t u p f o r th e in t e r f ace is as f o l l o w s: txd o f t h e 80c51/ 80l51 dr i v es scl k o f th e ad5025 /45/65, a nd rxd dr iv es th e s e r i al da ta lin e o f t h e pa r t . t h e sy n c s i g n a l i s ag a i n d e r i ve d f r om a bit - p ro g r am ma bl e p i n o n t h e p o r t . i n t h is cas e , p o r t l i ne p3 .3 is u s e d . w h en da t a is t o be t r a n s m i t t e d t o t h e ad502 5/45/65, p3.3 is tak e n lo w . th e 80c51/80l51 tr a n smi t da t a in 8 - b i t b y t e s o n l y ; t h us, o n l y eig h t falli n g c l ock edg e s occur i n t h e tra n s m i t c y c l e . t o loa d da ta t o t h e d a c, p3 .3 is lef t lo w a f t e r t h e f i rs t e i g h t b i t s a r e t r a n smi t t e d , a nd a s e co nd w r i t e c y cle is ini t i a te d to t r a n smi t t h e s e con d b y te o f da t a . p3.3 is t a k e n hig h fol l o w in g t h e com p let i o n o f t h is c y c l e . th e 80c5 1 /80l51 o u t p u t th e s e r i al da ta in a f o r m a t tha t has the ls b f i rst. th e ad5025/45/65 m u s t r e cei v e da t a wi th t h e m s b f i r s t . th e 8 0 c5 1/80l 51 tran smi t ro u t ine sho u l d ta k e t h is in t o accou n t. microprocessor interfacing ad5025/45/6 5 to black fi n ? adsp-bf53x interface f i gur e 48 sh o w s a s e r i al in t e r f ac e betw e e n t h e ad5025/45/65 a nd t h e bl ack fi n ad s p - b f53x micr op r o c e ss o r . the ads p - b f 53x p r o c esso r f a m i ly i n c o r p or a t e s t w o d u a l - c h a n n e l syn c hr on o u s s e r i al p o r t s, s p o r t1 an d s p or t0, fo r s e r i al a nd m u l t i p r o ce ss o r co mm un ic a t io ns. u s in g s p o r t0 t o co nn e c t t o th e ad5025 /45/65, th e s e t u p f o r th e in t e r f ace is as f o l l o w s: d t 0pri dr i v es th e d i n p i n o f t h e ad5025/45 /65, while tscl k 0 d r i v e s th e sc l k o f t h e pa r t s . t h e sy n c is dr i v en f r o m tf s0. ad s p -bf 5 3 x 1 tfs 0 dt o p r i t s cl k0 ad 50 65 / ad 50 45 / a d 50 25 1 syn c di n sc l k 000 0- 0 4 9 80 c 5 1/ 80l 5 1 1 p3 . 3 tx d rxd 1 a ddi t i o n al p i ns o m i t t e d f o r cl ar i t y . ad 50 65 /
ad 50 45 /
fi gur e 48 . ad5 025 /4 5/ 65 to bla c k fin a d sp-bf 5 3 x inte rfa ce ad5025/45/6 5 to 68hc11/6 8 l11 interface
f i gur e 49 sh o w s a s e r i al in t e r f ac e betw e e n t h e ad5025/45/65 a nd t h e 68h c1 1/68l11 micr o c o n tr ol ler . sck o f th e 68h c11/68l11 dr i v es t h e scl k o f the ad502 5/45/65, an d t h e mos i o u t p ut dr i v es t h e s e r i al da t a l i n e o f t h e d a c. 1 a d 50 25 syn c sc l k di n 00 00- 052 1 a ddi t i o n a l p i ns o m i t t e d f o r cl ari t y . ad5 0 6 5 / fi gur e 50 . ad5 025 /4 5/ 65 to 80 c512 /80 l 51 inter f a c e ad5 0 4 5 / ad5 0 2 5 / 1 ad5025/45/6 5 to microwire interface syn c 6 8 h c 1 1/68 l 1 1 1 pc 7 sc k mo si f i gur e 51 s h o w s a n i n t e r f a c e b e t w e e n t h e ad5025/45/65 a n d a n y sc l k mi cro w ire-co m p a t i b l e de vice . s e r i a l da t a is sh if te d o u t o n t h e di n fa l l in g e d ge o f t h e s e r i a l clock a n d is c l o c k e d in t o t h e ad5025/45 /65 o n t h e r i s i n g e d g e o f t h e s c l k . 00 00- 050 1 add i t i o nal p i ns o m i t t e d f o r cl a r i t y . a d 5 06 5/ mi c r o w i r e 1 a d 5 04 5/ fi gur e 49 . ad5 025 /4 5/ 65 t o 6 8 h c 11 /68 l 11 inter f a c e the sy n c sig n al is der i v e d f r o m a p o r t lin e (pc7). th e s e t u p co ndi t i on s fo r co r r e c t o p era t ion o f t h is i n t e r f ace a r e as fol l o w s: the 68h c11 / 68 l11 is co nf igur ed wi t h i t s cpo l b i t as 0, and i t s cp h a b i t as 1. w h en da t a is b e in g t r a n smi t t e d t o t h e d a c, t h e sy n c line is tak e n lo w (pc7). w h en th e 68 h c 11/ 68 l11 is co n f i g ur ed a s de scri bed p r evi o us l y , da ta a p pea r i n g o n t h e m o s i o u t p u t is valid o n t h e fal l i n g e d ge o f sck. s e r i al da ta f r o m t h e 68h c11/68l11 is tra n smi t t e d in 8-b i t b y t e s wi t h o n l y eig h t fa l l in g clo c k e d ges o c c u r r in g in t h e t r an smi t c y cle . d a t a is tra n smi t t e d ms b f i rs t. t o lo ad da ta t o the ad5 025/45/65, pc7 is lef t lo w a f t e r t h e f i rs t e i g h t b i t s a r e t r a n sfer r e d , a nd a s e co nd ad 50 25 cs syn c sk di n so sc l k 1 1 ad di t i o nal p i ns o m i t t e d f o r c l ari t y . fi gur e 51 . ad5 025 /4 5/ 65 4 to microwire inte r f a c e 0 000- 04 9 . 30 3 3
preliminary technical data ad5025/45/65
appli c a t ions using a reference as a power supply for this is a n ou t p u t v o l t a g e ra n g e o f 5 v , wi th 0x 0000 co r r e- the ad5025/45/6 5 s p o n din g t o a ? 5 v o u t p u t , an d 0xffff co r r es po n d i n g t o a b e c a u s e th e s u p p l y cu rr e n t r e q u i r ed b y th e ad5 025/45/65 i s +5 v o u t p u t . e x tr em e l y l o w , an a l te r n a t iv e opt i on i s to u s e a v o lt age re fe re nc e r2 = 10k ? +5 v C5v a d 820 / op2 9 5 ad 5 025 / 4 5 / 65 v dd v ou t r1 = 10k ? 5 v 0. 1 f 10 f to supply t h e r e q u ir e d v o l t a g e to t h e p a r t s (s e e f i g u re 5 2 ) . this is e s pe ci all y us ef u l if t h e p o w e r sup p ly is q u i t e n o i s y o r if t h e +5 v sys t em s u p p ly v o l t a g es a r e a t s o m e val u e o t h e r t h a n 5 v o r 3 v , fo r exa m ple , 15 v . th e v o l t a g e refer e n c e o u t p u t s a s t e a d y s u p p ly v o l t a g e f o r th e ad5025, ad50 45 a nd ad5065 . i f th e l o w dr op ou t ref19 5 is us ed , i t m u st s u p p l y 500 a o f c u r r en t t o the ad5025/ ad50 45 / ad5065, wi th n o lo ad on t h e o u t p u t o f the d a c. w h en t h e d a c o u t p u t is lo aded , t h e ref195 als o n eeds t o s u p p ly t h e c u r r en t t o t h e lo ad . th e t o t a l c u r r en t r e q u ir e d (wi t h a 5 k lo ad o n t h e d a c ou t p ut) is t hree - w i r e se ri al i n t e rf ace 500 a + (5 v/5 k) = 1.5 ma fi gur e 53 . bi pola r ope r a t i o n wi th the ad5 025 /4 5/ 65 the lo ad r e gu l a tio n o f t h e ref 195 is typ i cal l y 2 p p m /ma, using the ad5025/45/ 65 with a which r e s u l t s in a 3 p p m (15 v ) er r o r f o r th e 1.5 ma c u r r en t galvanica lly isolated interfa c e dra w n f r o m i t . this co r r es p o nds t o a 0.196 ls b er r o r . i n p r o c es s co n t r o l a p p l ica t io n s in ind u s t r i al en vir o nm en ts,
i t i s of te n ne c e s s ar y to u s e a g a lv ani c a l ly i s ol a t e d i n te r f ac e to
prote c t a n d i s o l a t e t h e c o n t ro l l i n g c i rc u i t r y f r o m a n y h a z a rd ou s co mm on- m o d e v o l t a g es t h a t can o c c u r i n t h e ar e a w h er e t h e d a c is f u n c t i o n ing. i c o u p l e r? p r o v ides is ol a t io n in excess o f 2.5 kv . th e ad5025/45/65 us es a 3-wir e s e r i a l log i c in t e r f ac e , s o t h e ad um13 00 t h r e e-cha n ne l dig i t a l is ol a t or p r o v ides t h e r e q u ir ed is o l a t io n (s ee f i gur e 5 4 ). the p o w e r su p p l y t o th e p a r t a d 506 5/ ad5 0 4 5 / ad5 0 2 5 t hre e- w i re ser i a l i n t e rf ac e sy nc sc l k di n 15 v 5v v ou t =0 vt o 5 v v dd re f 195 a l s o n e e d s t o b e is ola t e d , w h ich is do ne b y usin g a t r a n sfo r m e r . on t h e d a c side o f t h e t r a n sfo r m e r , a 5 v r e gu l a t o r p r o v i d es th e 5 v s u p p l y r e q u ir ed f o r the ad5025/45 /65. 000 0- 053 fi gur e 52 . ref19 5 a s po wer suppl y to the ad502 5/ 45 /65 bipolar operation using the ad5025/ 45/6 5 the ad5025 /45 / 65 has been desig n e d f o r sin g le-s u p p l y op e r a t i o n , bu t a b i p ola r o u t p ut r a n g e i s a l s o p o ss ib l e us ing t h e c i r c ui t i n f i gur e 53. th e c i r c ui t g i v e s a n o u t p u t v o l t a g e ra n g e o f 5 v . r a i l - t o-ra i l o p era t ion a t t h e am plif ier o u t p u t is achi e v ab l e 0. 1 f 5v r e g u la tor gn d di n syn c sc l k po w e r 10 f ad5 0 2 5/ 4 5 / 6 5 v ou t v ob v oa v oc v dd v ic v ib v ia a d u m 13 00 00 00- 055 usin g a n ad82 0 or an o p 295 as t h e ou tp u t am plif ier . sc l k the o u t p u t v o l t a g e fo r a n y in p u t co de ca n b e ca lc u l a t e d as fol l o w s: sd i a ?? ?? v dd d r1 r2 r2 v o v dd w h er e d r e p r es en ts t h e in p u t c o de in dec i mal (0 t o 65,535). wi t h v dd = 5 v , r1 = r2 = 10 k, ? ? 65 , 536 r1 r1 dat a fi gur e 54 . ad5 025 /4 5/ 65 wi th a ga l v ani c a l l y isol a t e d inter f a c e ?? ? 10 u d ?1 v o 5 v 65 , 536 rev. pr b ? page 31 of 3 3 0000 - 0 53
ad5025/45/65 preliminary technical data
outline dimensions
5.10 5.00 4.90 14 8 4.50 4.40 6.40 bsc 4.30 1 7 pin 1 1.05 0.65 1.00 0.15 0.30 bsc 0.20 1.20 0.80 0.75 8 max 0.09 0.60 0.05 seating 0 0.45 0.19 plane coplanarity 0.10 compliant to jedec standards mo-153-ab-1 fig u re 5 5 . 14-l e ad thin shr i nk s m a l l outlin e p a ck age [t ssop]
(r u - 14)
dim e nsio ns sho w n i n mi ll im e t er s
5.10 5.00 4.90 4.50 6.40 4.40 bsc 4.30 pin 1 0.15 16 9 8 1 1.20 max 0.20 0.05 0.75 0.09 0.60 0.65 0.30 0.19 seating 0 0.45 8 bsc plane coplanarity 0.10 compliant to jedec standards mo-153-ab fig u re 5 6 . 16-l e ad thin shr i nk s m a l l outlin e p a ck age [t ssop]
(r u - 16)
dim e nsio ns sho w n i n mi ll im e t er s
rev. pr b | page 32 of 3 3
preliminary technical data ad5025/45/65
ordering guide
model t e mper a t ur e r a nge p a ck age descri ption p a ck age op t i o n p o w e r- o n reset t o c o de acc u ra c y res o luti on ad5065bruz - 1 1 ?40c to +105c 14-l e ad tssop ru-14 z e r o 1 lsb inl 16 bits ad5065bruz - 1 r eel7 1 ?40c to +105c 14-l e ad tssop ru-14 z e r o 1 lsb inl 16 bits ad5045bruz 1 ?40c to +105c 16-l e ad tssop ru-16 z e r o 1 lsb inl 14 bits ad5045bruz - r eel7 1 ?40c to +105c 16-l e ad tssop ru-16 z e r o 1 lsb inl 14 bits ad5025bruz 1 ?40c to +105c 16-l e ad tssop ru-16 z e r o 1 lsb inl 12 bits ad5025bruz - r eel7 1 ?40c to +105c 16-l e ad tssop ru-16 z e r o 1 lsb inl 12 bits e v al- a d5065 ebz 1 e v alua tion boar d e v al- a d5045 ebz 1 e v alua tion boar d e v al- a d5025 ebz 1 e v alua tion boar d 1 z = pb-free part. ?2007 analo g devi ces, inc. all rights reserve d . tra d em ar ks and registered tra d emar ks are the prop erty of their respective o w ners . d06844-0-6/07(prb) rev. pr b | page 33 of 33

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